This invention relates to integer multiplication as employed in computers, and particularly to a method and apparatus for predicting overflow conditions in integer multiplication processes.
Integer overflow conditions occur when the result of an integer operation is physically larger than the resultant register in which it is to be stored. An overflow condition may occur in integer multiplication operations when the result of the integer multiplication operation on two or more operands is such as to create a resultant which exceeds the size of the resultant register. Heretofore, in integer multiplication apparatus, it has not been possible to predict an overflow condition simply by examination of the two input operands. Instead, it has been common in integer mathematics, to examine the resultant to determine if an overflow, condition has occurred. One problem with prior approaches is that sequentially performing the integer multiply and then, determining overflow, requires a substantial amount of time. This occurs because of the large volume of data resulting from the integer multiplication operation. It is desirable, therefore, to have a method and apparatus to predict overflow conditions in parallel with the performance of the integer multiply operation, so that an overflow condition is indicated as the result of the integer multiply ultimately is determined.
(Overflow prediction has been accomplished in floating-point multiply operations by adding the exponent, values of the floating point operands. Examples of such techniques may be found in the Blau et al. U.S. Pat. No. 4,429,370, Rosen U.S. Pat. No. 4,442,498, and Kobayashi et al. U.S. Pat. No. 4,534,010. However, because floating point operands contain exponents representative of the magnitude of the operand, such operands lend themselves well to prediction of overflow conditions. On the other hand, integer operands, which have no exponents, are not so suitable.)